mirror of https://github.com/YosysHQ/yosys.git
53ba3cf718
This brings the documented behavior for these cells in line with $_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S. The models were already reflecting that behavior. Also get rid of sim-synth mismatch in the models while we're at it. |
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| .. | ||
| .gitignore | ||
| Makefile.inc | ||
| abc9_model.v | ||
| adff2dff.v | ||
| cellhelp.py | ||
| cells.lib | ||
| cmp2lcu.v | ||
| cmp2lut.v | ||
| dff2ff.v | ||
| gate2lut.v | ||
| gen_fine_ffs.py | ||
| mul2dsp.v | ||
| pmux2mux.v | ||
| prep.cc | ||
| simcells.v | ||
| simlib.v | ||
| synth.cc | ||
| techmap.v | ||