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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 19:31:00 +02:00
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261daffd9d18adb13bb3dc53b17d3543109ea26c
yosys/techlibs/common
T
History
Eddie Hung e35dfc5ab5 Only swap ports if $mul and not $__mul
2019-08-13 16:52:15 -07:00
..
.gitignore
Added first help messages for cell types
2015-10-14 16:27:42 +02:00
adff2dff.v
Added adff2dff.v (for techmap -share_map)
2014-08-07 16:14:38 +02:00
cellhelp.py
Progress on cell help messages
2015-10-17 02:35:19 +02:00
cells.lib
Added cells.lib
2015-01-16 15:50:42 +01:00
cmp2lut.v
gen_lut to return correctly sized LUT mask
2019-07-16 12:45:29 -07:00
dff2ff.v
Add dff2ff.v techmap file
2017-05-31 11:45:58 +02:00
gate2lut.v
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
Makefile.inc
Add mul2dsp multiplier splitting rule and ECP5 mapping
2019-07-08 18:42:09 +01:00
mul2dsp.v
Only swap ports if $mul and not $__mul
2019-08-13 16:52:15 -07:00
pmux2mux.v
Added techlibs/common/pmux2mux.v
2014-01-17 20:06:15 +01:00
prep.cc
Add "wreduce -keepdc", fixes #1016
2019-05-20 15:36:13 +02:00
simcells.v
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
2019-08-06 04:47:55 +02:00
simlib.v
Reformat so it shows up/looks nice when "help $alu" and "help $alu+"
2019-08-09 12:33:39 -07:00
synth.cc
Revert "Add "synth -keepdc" option"
2019-07-09 10:14:23 -07:00
techmap.v
Added $ff and $_FF_ cell types
2016-10-12 01:18:39 +02:00
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