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25e33d7ab8ebeb96d6a7fb842e33f35770367587
yosys
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techlibs
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Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
...
Signed-off-by: Clifford Wolf <
[email protected]
>
2018-02-23 13:14:47 +01:00
..
achronix
Organizing Speedster file names
2017-11-08 20:23:55 -06:00
common
Add $allconst and $allseq cell types
2018-02-23 13:14:47 +01:00
coolrunner2
coolrunner2: Move LOC attributes onto the IO cells
2018-01-17 16:17:32 -08:00
easic
Add first draft of eASIC back-end
2017-09-29 17:53:43 +02:00
gowin
…
greenpak4
…
ice40
Fix port names in SB_IO_OD
2017-12-10 15:33:38 +00:00
intel
Add "dffinit -highlow" and fix synth_intel
2018-01-09 18:42:19 +01:00
xilinx
…
.gitignore
…