Clifford Wolf cc05404128 Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v

2013-05-24 15:15:59 +02:00

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asicworld

Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v

2013-05-24 15:15:59 +02:00

hana

added more .gitignore files (make test)

2013-01-05 11:35:52 +01:00

i2c_bench

initial import

2013-01-05 11:13:26 +01:00

k68_vltor

Now only use value from "initial" when no matching "always" block is found

2013-03-31 11:51:12 +02:00

no-icarus

initial import

2013-01-05 11:13:26 +01:00

simple

Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values

2013-04-13 21:19:10 +02:00

tools

Improved vcdcd.pl (added -d option)

2013-05-14 09:41:47 +02:00