Clifford Wolf 8a69759306 Add techlibs/xilinx/lut2lut.v		2017-07-10 12:09:05 +02:00
..
tests	…
.gitignore	…
Makefile.inc	Add techlibs/xilinx/lut2lut.v	2017-07-10 12:09:05 +02:00
arith_map.v	…
brams.txt	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
brams_bb.v	…
brams_init.py	Switched to Python 3	2015-08-22 09:59:33 +02:00
brams_map.v	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
cells_map.v	…
cells_sim.v	…
cells_xtra.sh	Added black box modules for all the 7-series design elements (as listed in ug953)	2016-03-19 11:09:10 +01:00
cells_xtra.v	Added black box modules for all the 7-series design elements (as listed in ug953)	2016-03-19 11:09:10 +01:00
drams.txt	…
drams_bb.v	…
drams_map.v	…
lut2lut.v	Add techlibs/xilinx/lut2lut.v	2017-07-10 12:09:05 +02:00
synth_xilinx.cc	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00