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luke
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yosys
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https://github.com/YosysHQ/yosys.git
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251285be4c086eba80cafe637029218bb2e8f2a7
yosys
/
techlibs
/
quicklogic
T
History
N. Engelhardt
303a386ecc
create duplicate IOFFs if multiple output ports are connected to the same register
2025-01-31 11:28:57 +01:00
..
common
…
pp3
…
qlf_k6n10f
Drop timestamp in generate_bram_types_sim.py
2024-10-30 08:47:18 +01:00
.gitignore
…
Makefile.inc
add ioff inference for qlf_k6n10f
2025-01-24 21:17:15 +01:00
ql_bram_merge.cc
Fix Windows build by forcing initialization order,
fixes
#4068
2024-01-02 11:26:48 +01:00
ql_bram_types.cc
…
ql_dsp_io_regs.cc
Fix Windows build by forcing initialization order,
fixes
#4068
2024-01-02 11:26:48 +01:00
ql_dsp_macc.cc
Fix out of tree build
2023-12-06 09:11:51 +01:00
ql_dsp_macc.pmg
…
ql_dsp_simd.cc
mark all hash_into methods nodiscard
2025-01-14 12:39:15 +01:00
ql_ioff.cc
create duplicate IOFFs if multiple output ports are connected to the same register
2025-01-31 11:28:57 +01:00
synth_quicklogic.cc
create duplicate IOFFs if multiple output ports are connected to the same register
2025-01-31 11:28:57 +01:00
