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aiger
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
alumacc
macc_v2: Add test
2025-01-27 13:19:26 +01:00
arch
analogdevices: Extra tests
2025-11-09 15:44:35 +00:00
asicworld
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
bind
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
blif
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
bram
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bugpoint
raise_error: don't rely on module ordering in test
2025-09-16 15:47:16 +02:00
cxxrtl
tests: replace CC and gcc with CXX and g++
2025-09-11 16:50:23 +02:00
errors
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
fmt
tests: replace CC and gcc with CXX and g++
2025-09-11 16:50:23 +02:00
fsm
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functional
read_verilog: add -relativeshare for synthesis reproducibility testing
2025-09-16 15:47:35 +02:00
hana
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
liberty
libparse: fix quoting and negedge in filterlib -verilogsim
2025-11-05 14:13:58 +01:00
lut
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
memfile
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memlib
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
memories
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
opt
Merge pull request #3991 from adrianparvino/alumacc-sign
2025-10-08 13:02:10 +02:00
opt_share
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peepopt
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
proc
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
pyosys
pyosys: fix regressions from 0.58
2025-10-26 02:21:40 +03:00
realmath
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rpc
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
rtlil
Don't stop parsing sigspec after a {} group.
2025-10-14 21:18:58 +00:00
sat
fix(parse): #5234 adjust width of rhs according to lhs
2025-09-16 15:24:23 +02:00
select
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
share
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sim
Revert sim's cycle_width default back to 10, but keep -width option
2025-10-20 14:40:05 +02:00
simple
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
simple_abc9
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
smv
Remove references to ilang
2024-11-05 12:36:31 +13:00
sva
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svinterfaces
tests/svinterfaces: re-chmod test script
2025-10-15 09:49:53 +13:00
svtypes
tests: remove -seq 1 from sat with -tempinduct where possible
2025-09-08 18:04:32 +02:00
techmap
Move global ABC configuration variables into AbcConfig and initialize them properly
2025-11-05 13:56:04 +00:00
tools
tests: replace CC and gcc with CXX and g++
2025-09-11 16:50:23 +02:00
unit
Merge pull request #5467 from YosysHQ/emil/liberty-unquoted-expressions
2025-11-06 19:45:17 +01:00
various
timeest: Add top ports launching/sampling
2025-11-03 14:21:28 +01:00
verific
Set `port_id` for Verific PortBus wires
2025-10-23 20:51:53 +00:00
verilog
tests: Fix for macos
2025-11-04 11:11:01 +13:00
vloghtb
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xprop
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.gitignore
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
gen-tests-makefile.sh
Update gen-tests-makefile.sh
2025-03-27 10:33:51 +13:00
09b5f610f7