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19 lines
644 B
Plaintext
19 lines
644 B
Plaintext
# Issue #5745: chparam values are unsigned when using read_verilog frontend
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#
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# When chparam overrides a parameter value, the signed attribute is lost,
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# causing signed comparisons to silently use unsigned logic.
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#
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# m = -32 (signed 9-bit), p2 = 11. Correct signed semantics: -32 < 11, so k = 1.
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# Bug: chparam strips the signed attribute from p2. The $lt cell gets A_SIGNED=0,
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# B_SIGNED=0, so the comparison treats m as unsigned (480 > 11), giving k = 0.
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read_verilog <<EOT
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module mod #(parameter p2=11) (output k);
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wire signed [8:0] m = -32;
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assign k = m < p2;
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endmodule
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EOT
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chparam -set p2 11
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hierarchy -top mod
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sat -prove k 1 -verify
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