mirror of https://github.com/YosysHQ/yosys.git
57 lines
1.2 KiB
Plaintext
57 lines
1.2 KiB
Plaintext
# Regression test: when procedural for-loops are unrolled, the constant
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# replacement for the loop variable must keep the variable's declared
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# signedness.
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read_verilog <<EOT
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module signed_index(input signed a, output reg y);
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reg signed i;
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always @*
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for (i = 1'h0; i < 1'h1; i = i + 1'h1)
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y = a <= i;
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endmodule
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EOT
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hierarchy -top signed_index
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proc
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sat -set a 1 -prove y 1 -verify
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design -reset
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# This loop runs more than once. The final assignment to y happens after the
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# step expression has recomputed i, so it fails unless the stepped value is
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# retagged with the loop variable's signedness too.
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read_verilog <<EOT
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module signed_index_after_step(input signed a, output reg y);
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reg signed [1:0] i;
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always @* begin
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y = 1'b0;
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for (i = -2'sd1; i < 2'sd1; i = i + 1'h1)
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y = a <= i;
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end
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endmodule
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EOT
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hierarchy -top signed_index_after_step
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proc
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sat -set a 1 -prove y 1 -verify
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design -reset
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# Control: `a` signed but `i` unsigned, so comparison should be unsigned.
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read_verilog <<EOT
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module unsigned_index(input signed a, output reg y);
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reg i;
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always @*
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for (i = 1'h0; i < 1'h1; i = i + 1'h1)
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y = a <= i;
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endmodule
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EOT
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hierarchy -top unsigned_index
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proc
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sat -set a 1 -prove y 0 -verify
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