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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 19:49:25 +02:00
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2093cf07e4b6fccd41da894e999acc8c528c06b3
yosys/techlibs
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gatecat b6467f0801 fabulous: Allow adding extra custom prims and map rules
Signed-off-by: gatecat <[email protected]>
2022-11-17 13:34:58 +01:00
..
achronix
Test fixes for latest iverilog
2022-09-21 15:46:43 +02:00
anlogic
anlogic: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
common
simlib: Simplify recently changed $mux model
2022-10-28 19:48:00 +02:00
coolrunner2
…
easic
…
ecp5
Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.
2022-06-02 23:16:12 +02:00
efinix
efinix: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
fabulous
fabulous: Allow adding extra custom prims and map rules
2022-11-17 13:34:58 +01:00
gatemate
Fix static initialization, fixes mingw build
2022-07-04 19:31:38 +02:00
gowin
Apicula now supports lutram
2022-07-03 12:45:03 +02:00
greenpak4
…
ice40
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
intel
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
intel_alm
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
machxo2
machxo2: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
nexus
nexus: Fix BRAM mapping.
2022-08-09 23:47:55 +02:00
quicklogic
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
sf2
Test fixes for latest iverilog
2022-09-21 15:46:43 +02:00
xilinx
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
.gitignore
…
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