mirror of https://github.com/YosysHQ/yosys.git
44 lines
697 B
Verilog
44 lines
697 B
Verilog
module dffe_00( input clk, en,
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input d1, output reg q1,
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);
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always @( negedge clk ) begin
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if ( ~en )
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q1 <= d1;
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end
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endmodule
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module dffe_01( input clk, en,
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input d1, output reg q1,
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);
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always @( negedge clk ) begin
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if ( en )
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q1 <= d1;
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end
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endmodule
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module dffe_10( input clk, en,
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input d1, output reg q1,
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);
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always @( posedge clk ) begin
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if ( ~en )
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q1 <= d1;
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end
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endmodule
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module dffe_11( input clk, en,
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input d1, output reg q1,
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);
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always @( posedge clk ) begin
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if ( en )
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q1 <= d1;
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end
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endmodule
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module dffe_wide_11( input clk, en,
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input [3:0] d1, output reg [3:0] q1,
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);
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always @( posedge clk ) begin
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if ( en )
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q1 <= d1;
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end
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endmodule |