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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 02:57:40 +02:00
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1eea06bcc0750de02a460f3e949df2f68f800382
yosys/techlibs
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gatecat 34a08750fa intel_alm: Fix illegal carry chains
Signed-off-by: gatecat <[email protected]>
2021-05-15 22:37:06 +01:00
..
achronix
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
anlogic
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
common
abc9: fix SCC issues (#2694)
2021-03-29 22:01:57 -07:00
coolrunner2
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
easic
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
ecp5
Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib.
2021-05-12 10:04:34 +01:00
efinix
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
gowin
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
greenpak4
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
ice40
Add default assignments to other SB_* simulation models
2021-04-20 18:52:36 +02:00
intel
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
intel_alm
intel_alm: Fix illegal carry chains
2021-05-15 22:37:06 +01:00
machxo2
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
nexus
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
quicklogic
quicklogic: ABC9 synthesis
2021-04-17 20:54:58 +02:00
sf2
sf2: fix name of AND modules
2021-04-09 16:46:05 +02:00
xilinx
Fix use of blif name in synth_xilinx command
2021-04-27 02:29:52 -07:00
.gitignore
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