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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 09:30:28 +02:00
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1ecf6aee9b331efebeca1bd95a3d5125abf8da50
yosys/tests/proc
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Marcelina Kościelnicka 9450f308f0 proc_rom: Add special handling of const-0 address bits.
2022-05-18 17:32:30 +02:00
..
.gitignore
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
bug2619.ys
proc_dff: Fix emitted FF when a register is not assigned in async reset
2021-03-08 17:01:43 +01:00
bug2656.ys
proc_arst: Add special-casing of clock signal in conditionals.
2021-03-15 17:17:29 +01:00
bug2962.ys
proc_prune: Make assign removal and promotion per-bit, remember promoted bits.
2021-08-14 15:26:11 +02:00
bug_1268.v
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
bug_1268.ys
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
proc_rom.ys
proc_rom: Add special handling of const-0 address bits.
2022-05-18 17:32:30 +02:00
rmdead.v
proc_rmdead: use explicit pattern set when there are no wildcards
2021-07-29 20:55:59 -04:00
rmdead.ys
proc_rmdead: use explicit pattern set when there are no wildcards
2021-07-29 20:55:59 -04:00
run-test.sh
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
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