yosys/passes
Emil J. Tywoniak 1da5f4dfef techmap: disable signorm more 2026-05-05 21:35:13 +02:00
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cmds check: don't fail on $input_port 2026-05-05 21:35:13 +02:00
equiv Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 2026-03-04 14:47:57 +00:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy hierarchy.cc: Tidying 2025-10-15 09:42:47 +13:00
memory memory_libmap: Add -force-params 2026-02-20 10:57:00 +00:00
opt opt_hier: disable signorm 2026-05-05 21:35:13 +02:00
pmgen Fix typo in pmgen/README.md 2026-04-02 10:24:31 -05:00
proc proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
sat Add comments to make sure it is clear scale is an exponent of 10 2026-04-23 17:22:14 +01:00
techmap techmap: disable signorm more 2026-05-05 21:35:13 +02:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00