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21 lines
325 B
Systemverilog
21 lines
325 B
Systemverilog
module gold(a, b);
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output wire [1:0] a;
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input wire [1:0] b;
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genvar i;
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for (i = 0; i < 2; i++) begin
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wire x;
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assign x = b[i];
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assign a[i] = x;
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end
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endmodule
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module gate(a, b);
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output wire [1:0] a;
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input wire [1:0] b;
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genvar i;
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for (i = 0; i < 2; i++) begin
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assign x = b[i];
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assign a[i] = x;
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end
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endmodule
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