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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-07 10:32:59 +02:00
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1d3f9b79052d3330a0c2f2e8f27cfd13b7e01af4
yosys/frontends/verilog
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Emil J. Tywoniak 83c1364eeb read_verilog: remove log I left behind by accident
2026-01-13 18:47:23 +01:00
..
.gitignore
read_verilog, ast: use unified locations in errors and simplify dependencies
2025-08-11 13:34:10 +02:00
const2ast.cc
Remove .c_str() calls from parameters to log_file_warning()
2025-09-16 23:03:45 +00:00
Makefile.inc
verilog: fix build dependency graph
2025-08-11 13:34:10 +02:00
preproc.cc
reduce OS ifdefs, refactor getting dirs and filenames from paths to files
2025-10-14 15:46:17 +02:00
preproc.h
preproc: formatting
2025-08-11 13:34:10 +02:00
verilog_error.cc
Use C++ stringf machinery in verilog_error
2025-09-12 06:21:56 +00:00
verilog_error.h
Use C++ stringf machinery in verilog_error
2025-09-12 06:21:56 +00:00
verilog_frontend.cc
read_verilog: remove log I left behind by accident
2026-01-13 18:47:23 +01:00
verilog_frontend.h
const2ast: fix for consistency with previous diagnostics behavior
2025-08-11 13:34:10 +02:00
verilog_lexer.h
verilog_lexer: refactor
2025-08-11 13:34:10 +02:00
verilog_lexer.l
verilog: Bufnorm cell backend and frontend support
2025-09-17 14:01:09 +02:00
verilog_location.h
verilog: Fix missing sstream include
2025-08-21 08:26:20 +01:00
verilog_parser.y
no use vector
2025-11-08 23:16:52 +05:30
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