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yosys
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1bf7a18fec76cf46a5b8710a75371e23b68d147d
yosys
/
passes
/
techmap
T
History
Clifford Wolf
1bf7a18fec
Added module->ports
2014-08-14 16:22:52 +02:00
..
.gitignore
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
dfflibmap.cc
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
extract.cc
Added module->ports
2014-08-14 16:22:52 +02:00
filterlib.cc
…
hilomap.cc
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
iopadmap.cc
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
libparse.cc
…
libparse.h
…
Makefile.inc
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
simplemap.cc
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
techmap.cc
Implemented recursive techmap
2014-08-03 12:40:43 +02:00
