yosys/frontends/verilog
Akash Levy 1b3375d8df Merge upstream in 2025-09-09 05:50:48 -07:00
..
.gitignore read_verilog, ast: use unified locations in errors and simplify dependencies 2025-08-11 13:34:10 +02:00
Makefile.inc verilog: fix build dependency graph 2025-08-11 13:34:10 +02:00
const2ast.cc const2ast: fix for consistency with previous diagnostics behavior 2025-08-11 13:34:10 +02:00
preproc.cc Merge upstream in 2025-09-09 05:50:48 -07:00
preproc.h preproc: formatting 2025-08-11 13:34:10 +02:00
verilog_error.cc verilog: demote some parser errors to warnings again 2025-08-13 10:54:47 +02:00
verilog_error.h verilog: demote some parser errors to warnings again 2025-08-13 10:54:47 +02:00
verilog_frontend.cc verilog_location: rename location to Location to avoid conflict with Pass::location 2025-08-11 13:34:10 +02:00
verilog_frontend.h const2ast: fix for consistency with previous diagnostics behavior 2025-08-11 13:34:10 +02:00
verilog_lexer.h verilog_lexer: refactor 2025-08-11 13:34:10 +02:00
verilog_lexer.l verilog_lexer, verilog_parser: remove comment 2025-08-11 13:34:10 +02:00
verilog_location.h verilog: Fix missing sstream include 2025-08-21 08:26:20 +01:00
verilog_parser.y Merge upstream in 2025-09-09 05:50:48 -07:00