Eddie Hung a270af00cc Put abc_* attributes above port		2019-08-23 11:21:44 -07:00
..
tests	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"	2019-08-12 12:06:45 -07:00
.gitignore	…
Makefile.inc	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"	2019-08-12 12:06:45 -07:00
abc_hx.box	…
abc_hx.lut	…
abc_lp.box	…
abc_lp.lut	…
abc_u.box	…
abc_u.lut	…
arith_map.v	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"	2019-08-12 12:06:45 -07:00
brams.txt	…
brams_init.py	…
brams_map.v	…
cells_map.v	Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER	2019-08-12 12:19:25 -07:00
cells_sim.v	Put abc_* attributes above port	2019-08-23 11:21:44 -07:00
ice40_braminit.cc	substr() -> compare()	2019-08-07 12:20:08 -07:00
ice40_ffinit.cc	…
ice40_ffssr.cc	…
ice40_opt.cc	…
latches_map.v	…
synth_ice40.cc	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"	2019-08-12 12:06:45 -07:00