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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 12:21:16 +02:00
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18cabe9370c46b72e9fb52eb9be5a7c7fb873274
yosys/techlibs
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Eddie Hung 9314a0a42e Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
2019-08-28 10:51:39 -07:00
..
achronix
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
anlogic
Fix missing newline at end of file
2019-08-22 18:09:37 +02:00
common
Missing newline
2019-08-20 20:37:52 -07:00
coolrunner2
Fix spacing
2019-08-06 16:47:55 -07:00
easic
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
ecp5
ecp5: Add GSR support
2019-08-27 13:07:06 +01:00
efinix
Fix missing newline at end of file
2019-08-22 18:06:36 +02:00
gowin
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
greenpak4
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
ice40
Put abc_* attributes above port
2019-08-23 11:21:44 -07:00
intel
techlibs/intel: Clean up Makefile
2019-08-05 11:22:11 -07:00
sf2
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
xilinx
Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
2019-08-28 10:51:39 -07:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
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