mirror of https://github.com/YosysHQ/yosys.git
25 lines
398 B
Verilog
25 lines
398 B
Verilog
module fir_4tap(
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input clk,
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input [15:0] x,
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input [15:0] c0, c1, c2, c3,
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output reg [31:0] y
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);
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reg [15:0] x1, x2, x3;
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always @(posedge clk) begin
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x1 <= x;
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x2 <= x1;
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x3 <= x2;
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end
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wire [31:0] p0 = x * c0;
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wire [31:0] p1 = x1 * c1;
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wire [31:0] p2 = x2 * c2;
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wire [31:0] p3 = x3 * c3;
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wire [31:0] sum = p0 + p1 + p2 + p3;
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always @(posedge clk)
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y <= sum;
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endmodule
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