mirror of https://github.com/YosysHQ/yosys.git
28 lines
431 B
Verilog
28 lines
431 B
Verilog
module equiv_sub_mixed(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b - c + d;
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endmodule
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module equiv_sub_all(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a - b - c - d;
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endmodule
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module equiv_sub_3op(
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input [3:0] a, b, c,
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output [3:0] y
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);
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assign y = a - b + c;
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endmodule
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module equiv_sub_signed(
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input signed [3:0] a, b, c, d,
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output signed [5:0] y
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);
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assign y = a + b - c - d;
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endmodule
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