mirror of https://github.com/YosysHQ/yosys.git
42 lines
901 B
Plaintext
42 lines
901 B
Plaintext
# Test equiv_opt on narrow sub designs
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read_verilog equiv_sub_narrow.v
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hierarchy -top equiv_sub_mixed
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proc; opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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log "equiv_sub_mixed: ok"
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read_verilog equiv_sub_narrow.v
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hierarchy -top equiv_sub_all
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proc; opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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log "equiv_sub_all: ok"
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read_verilog equiv_sub_narrow.v
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hierarchy -top equiv_sub_3op
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proc; opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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log "equiv_sub_3op: ok"
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read_verilog equiv_sub_narrow.v
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hierarchy -top equiv_sub_signed
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proc; opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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log "equiv_sub_signed: ok"
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