This website requires JavaScript.
Explore
Help
Register
Sign In
luke
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Packages
Projects
Releases
Wiki
Activity
18c7cb094e
yosys
/
tests
/
csa_tree
/
add_repeated.v
7 lines
94 B
Verilog
Raw
Blame
History
module
add_repeated
(
input
[
7
:
0
]
a
,
output
[
7
:
0
]
y
)
;
assign
y
=
a
+
a
+
a
+
a
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink