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20 lines
586 B
Systemverilog
20 lines
586 B
Systemverilog
// Reference: equivalent design WITHOUT variable-part-select.
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module opt_vps_byte_write (
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input logic clk,
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input logic wr_en,
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input logic [1:0] lane,
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input logic [7:0] wdata,
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output logic [31:0] q
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);
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logic [31:0] reg_data;
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always_ff @(posedge clk)
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if (wr_en)
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case (lane)
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2'd0: reg_data[ 7: 0] <= wdata;
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2'd1: reg_data[15: 8] <= wdata;
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2'd2: reg_data[23:16] <= wdata;
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2'd3: reg_data[31:24] <= wdata;
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endcase
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assign q = reg_data;
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endmodule
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