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15 lines
422 B
Systemverilog
15 lines
422 B
Systemverilog
// 32-bit register with byte-lane writes indexed by a 2-bit selector (VPS).
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module opt_vps_byte_write (
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input logic clk,
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input logic wr_en,
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input logic [1:0] lane,
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input logic [7:0] wdata,
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output logic [31:0] q
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);
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logic [31:0] reg_data;
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always_ff @(posedge clk)
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if (wr_en)
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reg_data[((lane + 1) * 8) - 1 -: 8] <= wdata;
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assign q = reg_data;
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endmodule
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