yosys/techlibs/common
Eddie Hung ab46d9017b Fix signedness bug 2019-09-20 10:11:36 -07:00
..
.gitignore
Makefile.inc Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-05 13:01:27 -07:00
adff2dff.v
cellhelp.py
cells.lib
cmp2lut.v gen_lut to return correctly sized LUT mask 2019-07-16 12:45:29 -07:00
dff2ff.v
dummy.box Use a dummy box file if none specified 2019-08-28 20:58:55 -07:00
gate2lut.v
mul2dsp.v Fix signedness bug 2019-09-20 10:11:36 -07:00
pmux2mux.v
prep.cc Add "wreduce -keepdc", fixes #1016 2019-05-20 15:36:13 +02:00
simcells.v Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 2019-08-06 04:47:55 +02:00
simlib.v Reformat so it shows up/looks nice when "help $alu" and "help $alu+" 2019-08-09 12:33:39 -07:00
synth.cc Missing newline 2019-08-20 20:37:52 -07:00
techmap.v