yosys/passes/techmap
YRabbit f5609d52c4 Correct a typo in the manual
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-02-02 21:14:38 +10:00
..
Makefile.inc Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
abc.cc Spelling fix in abc.cc 2021-11-10 16:47:54 +01:00
abc9.cc
abc9_exe.cc
abc9_ops.cc sta: very crude static timing analysis pass 2021-11-25 17:20:27 +01:00
aigmap.cc
alumacc.cc
attrmap.cc
attrmvcp.cc
bmuxmap.cc Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
clkbufmap.cc
deminout.cc
demuxmap.cc Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
dffinit.cc
dfflegalize.cc dfflegalize: Refactor, add aldff support. 2021-10-27 14:14:01 +02:00
dfflibmap.cc
dffunmap.cc
extract.cc
extract_counter.cc
extract_fa.cc
extract_reduce.cc Change implicit conversions from bool to Sig* to explicit. 2021-10-21 20:20:31 +02:00
extractinv.cc
filterlib.cc
flatten.cc flatten: Keep sigmap around between flatten_cell invocations. 2021-11-02 13:18:15 +01:00
flowmap.cc
hilomap.cc
insbuf.cc
iopadmap.cc Correct a typo in the manual 2022-02-02 21:14:38 +10:00
libparse.cc
libparse.h
lut2mux.cc
maccmap.cc
muxcover.cc
nlutmap.cc
pmuxtree.cc
shregmap.cc
simplemap.cc Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
simplemap.h
techmap.cc verilog: use derived module info to elaborate cell connections 2021-10-25 18:25:50 -07:00
tribuf.cc
zinit.cc