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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 09:30:28 +02:00
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1733a76273bcd7ca46fd47ab2ab706b8eb13bdf4
yosys/frontends
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History
Miodrag Milanovic d473a207a1 Preserve VHDL architecture name in attribute
2023-10-12 09:17:06 +02:00
..
aiger
…
ast
ast/simplify: Remove unused in_param code
2023-10-05 22:42:36 -04:00
blif
fix whitespace
2022-10-10 16:31:29 +02:00
json
fix handling of escaped chars in json backend and frontend
2022-02-18 17:13:09 +01:00
liberty
print filename in liberty log_header
2023-01-11 21:31:46 +01:00
rpc
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
rtlil
Specify minimum bison version 3.0+
2021-10-01 21:18:33 -06:00
verific
Preserve VHDL architecture name in attribute
2023-10-12 09:17:06 +02:00
verilog
fix width of post-increment/decrement expressions
2023-09-18 23:46:06 -04:00
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