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luke
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yosys
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https://github.com/YosysHQ/yosys.git
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1723aa251afa492898b4046ff4dc867a1265d6c5
yosys
/
techlibs
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intel
T
History
Richard Herveille
1723aa251a
Added DSP support and updates for performance
2024-03-06 02:45:40 +01:00
..
common
Fixed data/address width parameters
2024-03-06 02:45:07 +01:00
cyclone10lp
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cycloneiv
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cycloneive
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
max10
Added DSP macros
2024-03-06 02:45:29 +01:00
Makefile.inc
synth_intel: Remove incomplete Arria 10 GX support.
2020-08-21 01:46:06 +02:00
synth_intel.cc
Added DSP support and updates for performance
2024-03-06 02:45:40 +01:00
