yosys/techlibs at 1602516a8b2ebd432528e9ba39a00db4e6edc081 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 11:18:31 +02:00

Files

T

History

Eddie Hung 1602516a8b $__ABC_REG to have WIDTH parameter

2019-09-19 19:37:45 -07:00

..

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

make note that it is for latch mode

2019-09-18 17:48:16 +02:00

Be sensitive to signedness

2019-09-10 15:14:55 -07:00

Fix spacing

2019-08-06 16:47:55 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Merge remote-tracking branch 'origin/master' into xc7dsp

2019-09-05 13:01:27 -07:00

better handling of lut and begin/end add

2019-09-18 17:45:07 +02:00

Fix formatting for msys2 mingw build using GetSize

2019-08-01 17:27:34 +02:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2

2019-09-19 14:57:38 -07:00

techlibs/intel: Clean up Makefile

2019-08-05 11:22:11 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

$__ABC_REG to have WIDTH parameter

2019-09-19 19:37:45 -07:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00