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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 01:24:25 +02:00
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14ce8bdaa6a1120c48a934697488c463ffb15b48
yosys/techlibs
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Marcelina Kościelnicka cde73428b0 Fix syntax error in adff2dff.v
Fixes #2600.
2021-02-24 01:07:34 +01:00
..
achronix
achronix: Use dfflegalize.
2020-07-14 23:12:16 +02:00
anlogic
anlogic: Fix FF mapping.
2020-07-17 14:03:21 +02:00
common
Fix syntax error in adff2dff.v
2021-02-24 01:07:34 +01:00
coolrunner2
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
easic
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
ecp5
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
efinix
techmap: Add support for [] wildcards in techmap_celltype.
2020-08-02 22:46:48 +02:00
gowin
add -noalu and -json option for apicula
2020-11-30 11:43:12 +01:00
greenpak4
opt_expr: Remove -clkinv option, make it the default.
2020-07-31 00:08:15 +02:00
ice40
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
intel
Fix duplicated parameter name typo
2020-11-18 10:03:57 +01:00
intel_alm
intel_alm: better map wide but shallow multiplies
2020-08-28 23:44:16 +02:00
machxo2
machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.
2021-02-23 17:39:58 +01:00
nexus
nexus: Add MULTADDSUB9X9WIDE sim model
2020-12-08 15:49:20 +00:00
sf2
sf2: Emit CLKINT even if -clkbuf not passed
2020-07-17 15:01:47 +02:00
xilinx
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
.gitignore
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