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1482f32d53da84ddfb034cff88174af5e5c41761
yosys/techlibs/xilinx
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Eddie Hung 10e82e103f Revert "Optimise write_xaiger"
2019-12-20 12:05:45 -08:00
..
tests
…
.gitignore
…
abc9_map.v
abc9_map.v: fix Xilinx LUTRAM
2019-12-12 14:56:52 -08:00
abc9_model.v
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_unmap.v
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_xc7_nowide.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_xc7.box
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_xc7.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
arith_map.v
…
brams_init.py
…
cells_map.v
xilinx: Improve flip-flop handling.
2019-12-18 13:43:43 +01:00
cells_sim.v
xilinx: Add simulation models for remaining CLB primitives.
2019-12-19 18:04:04 +01:00
cells_xtra.py
xilinx: Add simulation models for remaining CLB primitives.
2019-12-19 18:04:04 +01:00
cells_xtra.v
xilinx: Add simulation models for remaining CLB primitives.
2019-12-19 18:04:04 +01:00
lut_map.v
xilinx: Use INV instead of LUT1 when applicable
2019-11-25 20:40:39 +01:00
lutrams_map.v
Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram
2019-12-16 12:06:47 -08:00
lutrams.txt
Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q
2019-12-16 10:41:13 -08:00
Makefile.inc
xilinx: Add xilinx_dffopt pass (#1557)
2019-12-18 13:43:43 +01:00
mux_map.v
…
synth_xilinx.cc
Revert "Optimise write_xaiger"
2019-12-20 12:05:45 -08:00
xc3s_mult_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc3sda_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc4v_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc5v_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc6s_brams_map.v
…
xc6s_brams.txt
…
xc6s_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc6s_ff_map.v
xilinx: Improve flip-flop handling.
2019-12-18 13:43:43 +01:00
xc7_brams_map.v
…
xc7_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc7_ff_map.v
xilinx: Improve flip-flop handling.
2019-12-18 13:43:43 +01:00
xc7_xcu_brams.txt
Add unconditional match blocks for force RAM
2019-12-16 13:31:15 -08:00
xcu_brams_map.v
xilinx: Add support for UltraScale[+] BRAM mapping
2019-10-23 11:47:37 +01:00
xcu_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xcup_urams_map.v
xilinx: Add URAM288 mapping for xcup
2019-10-23 11:47:44 +01:00
xcup_urams.txt
xilinx: Add URAM288 mapping for xcup
2019-10-23 11:47:44 +01:00
xilinx_dffopt.cc
xilinx_dffopt: Keep order of LUT inputs.
2019-12-19 18:01:43 +01:00