mirror of https://github.com/YosysHQ/yosys.git
134 lines
2.6 KiB
Plaintext
134 lines
2.6 KiB
Plaintext
log -header "Simple positive case (negation on port B)"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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output wire signed [7:0] y;
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assign y = a + (-b);
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -post
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design -load postopt
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select -assert-count 1 t:$sub
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select -assert-none t:$add
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select -assert-none t:$neg
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design -reset
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log -pop
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log -header "Positive case (negation on port A)"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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output wire signed [7:0] y;
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assign y = (-a) + b;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -post
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design -load postopt
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select -assert-count 1 t:$sub
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select -assert-none t:$add
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select -assert-none t:$neg
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design -reset
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log -pop
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log -header "Unsigned positive case"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire [7:0] a;
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input wire [7:0] b;
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output wire [7:0] y;
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assign y = a + (-b);
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -post
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design -load postopt
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select -assert-count 1 t:$sub
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select -assert-none t:$add
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select -assert-none t:$neg
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design -reset
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log -pop
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log -header "Negative case: output wider than negation"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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output wire signed [8:0] y;
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wire signed [7:0] nb;
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assign nb = -b;
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assign y = a + nb;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -post
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 1 t:$neg
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Negative case: negation truncates input"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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output wire signed [3:0] y;
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wire signed [3:0] nb;
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assign nb = -b;
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assign y = a[3:0] + nb;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -post
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 1 t:$neg
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Negative case: neg output has extra fanout"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y, z);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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output wire signed [7:0] y;
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output wire signed [7:0] z;
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(* keep *) wire signed [7:0] nb;
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assign nb = -b;
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assign y = a + nb;
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assign z = nb;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -post
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 1 t:$neg
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select -assert-none t:$sub
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design -reset
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log -pop
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