yosys/examples/intel at 142f4ca03a65bd590e6d17be8fbcf3e6a793febe - yosys - Gitea: Git with a cup of tea

luke/yosys

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Clifford Wolf b72a7e1104 Replace CRLF line endings with LF in de2i.qsf (quartus example)

2017-04-12 16:51:46 +02:00

..

Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs

2017-04-05 23:01:29 -05:00

Replace CRLF line endings with LF in de2i.qsf (quartus example)

2017-04-12 16:51:46 +02:00

Squelch trailing whitespace

2017-04-12 15:11:09 +02:00