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yosys/tests/verilog
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Eddie Hung 5bcde7ccc3 Merge pull request #2045 from YosysHQ/eddie/fix2042 
verilog: error if no direction given for task arguments, default to input in SV mode
2020-05-14 09:45:54 -07:00
..
.gitignore
Setup tests/verilog properly
2020-05-11 10:31:02 -07:00
bug2042-sv.ys
test: add another testcase as per @nakengelhardt
2020-05-14 08:36:36 -07:00
bug2042.ys
tests: update/extend task argument tests
2020-05-13 10:11:45 -07:00
run-test.sh
Setup tests/verilog properly
2020-05-11 10:31:02 -07:00
upto.ys
techlibs/common: more robustness when *_WIDTH = 0
2020-05-05 08:01:27 -07:00