yosys/techlibs/intel
Catherine a727e7f6e7 Migrate build system to CMake
See #5895 for details.

This commit does not include CI or documentation changes.
2026-06-03 08:58:10 +00:00
..
common Fixed data/address width parameters 2024-03-06 02:45:07 +01:00
cyclone10lp Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
cycloneiv Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
cycloneive Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
max10 Removed SystemVerilog module end label 2024-03-19 01:31:36 +01:00
CMakeLists.txt Migrate build system to CMake 2026-06-03 08:58:10 +00:00
synth_intel.cc Add check before flatten in synth_*. 2026-05-05 14:06:58 +02:00