yosys/techlibs/anlogic
Catherine a727e7f6e7 Migrate build system to CMake
See #5895 for details.

This commit does not include CI or documentation changes.
2026-06-03 08:58:10 +00:00
..
CMakeLists.txt Migrate build system to CMake 2026-06-03 08:58:10 +00:00
anlogic_eqn.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
anlogic_fixcarry.cc Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
arith_map.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
brams.txt anlogic: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
brams_map.v anlogic: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
cells_map.v anlogic: Fix FF mapping. 2020-07-17 14:03:21 +02:00
cells_sim.v anlogic: Use dfflegalize. 2020-07-14 05:02:50 +02:00
eagle_bb.v Revert "Leave only real black box cells" 2018-12-17 23:20:40 +08:00
lutrams.txt anlogic: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
lutrams_map.v anlogic: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
synth_anlogic.cc Add check before flatten in synth_*. 2026-05-05 14:06:58 +02:00