mirror of https://github.com/YosysHQ/yosys.git
34 lines
685 B
Plaintext
34 lines
685 B
Plaintext
read_verilog -sv << EOF
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interface simple_if;
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logic receiver;
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logic driver;
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endinterface
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module driver_mod(simple_if intf, input in);
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assign intf.driver = in;
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endmodule
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module receiver_mod(simple_if intf);
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assign intf.receiver = intf.driver;
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endmodule
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module top(
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input logic [1:0] inputs,
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output logic [1:0] outputs
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);
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simple_if intf0();
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simple_if intf1();
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driver_mod d0(intf0, inputs[0]);
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driver_mod d1(intf1, inputs[1]);
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receiver_mod r0(intf0);
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receiver_mod r1(intf1);
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assign outputs = {intf0.receiver, intf1.receiver};
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endmodule
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EOF
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logger -expect error "Unable to connect.* with positional interface" 1
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hierarchy -top top
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