yosys/frontends/verilog
Miodrag Milanovic b76c72056b set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
..
.gitignore
Makefile.inc
const2ast.cc
preproc.cc set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
preproc.h verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
verilog_frontend.cc verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_frontend.h verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_lexer.l verilog: support for time scale delay values 2022-02-14 15:58:31 +01:00
verilog_parser.y verilog: support for time scale delay values 2022-02-14 15:58:31 +01:00