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Ruben Undheim d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00
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run-test.sh Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00
runone.sh Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00
svinterface1.sv Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00
svinterface1_ref.v Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00
svinterface1_tb.v Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00