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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 03:52:06 +02:00
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10d0bad67e91c45813a1185753fa4dcbcc2c86d8
yosys/techlibs
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History
Eddie Hung b47bb5c810 Fix typo in check_label()
2019-10-04 21:43:50 -07:00
..
achronix
…
anlogic
make note that it is for latch mode
2019-09-18 17:48:16 +02:00
common
Missing (* mul2dsp *) for sliceB
2019-09-27 14:21:47 -07:00
coolrunner2
Fix spacing
2019-08-06 16:47:55 -07:00
easic
…
ecp5
Panic over. Model was elsewhere. Re-arrange for consistency
2019-10-04 10:48:44 -07:00
efinix
better handling of lut and begin/end add
2019-09-18 17:45:07 +02:00
gowin
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
greenpak4
…
ice40
Panic over. Model was elsewhere. Re-arrange for consistency
2019-10-04 10:48:44 -07:00
intel
techlibs/intel: Clean up Makefile
2019-08-05 11:22:11 -07:00
sf2
…
xilinx
Fix typo in check_label()
2019-10-04 21:43:50 -07:00
.gitignore
…
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