yosys/techlibs at 107d8848041289bdf3ed85f2ca6c7e02fa9ec774 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-01 02:27:34 +02:00

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Miodrag Milanovic ca2b3feed8 Fix ECP5 cells_sim for iverilog

2019-03-01 19:25:23 +01:00

..

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

Merge pull request #772 from whitequark/synth_lut

2019-01-02 15:44:57 +01:00

Unify usage of noflatten among architectures

2019-01-04 11:37:25 +01:00

Fix typographical and grammatical errors and inconsistencies.

2019-01-02 13:12:17 +00:00

Fix ECP5 cells_sim for iverilog

2019-03-01 19:25:23 +01:00

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module

2019-02-26 09:40:46 -08:00

ice40: use 2 bits for READ/WRITE MODE for SB_RAM map

2019-02-28 16:23:40 -08:00

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

Add SF2 IO buffer insertion

2019-01-17 14:38:37 +01:00

Fix typographical and grammatical errors and inconsistencies.

2019-01-02 13:12:17 +00:00

.gitignore

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