yosys/techlibs at 101235400caeb4ec019311dfb96100b770060c92 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 03:23:11 +02:00

Files

T

History

whitequark 101235400c Merge branch 'master' into eddie/pr1266_again

2019-08-18 08:04:10 +00:00

..

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

anlogic : Fix alu mapping

2019-08-03 14:47:33 +02:00

Reformat so it shows up/looks nice when "help $alu" and "help $alu+"

2019-08-09 12:33:39 -07:00

Fix spacing

2019-08-06 16:47:55 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

ecp5: Make cells_sim.v consistent with nextpnr

2019-08-07 14:19:31 +01:00

Fix formatting for msys2 mingw build using GetSize

2019-08-01 17:27:34 +02:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER

2019-08-12 12:19:25 -07:00

techlibs/intel: Clean up Makefile

2019-08-05 11:22:11 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

stoi -> atoi

2019-08-07 11:09:17 -07:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00