mirror of https://github.com/YosysHQ/yosys.git
178 lines
4.2 KiB
Verilog
178 lines
4.2 KiB
Verilog
// Rising edge DFF
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module \$_DFF_P_ (D, C, Q);
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input D;
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input C;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
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endmodule
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// Rising edge DFF with async active-high reset
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module \$_DFF_PP0_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
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endmodule
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// Rising edge DFF with async active-high set
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module \$_DFF_PP1_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
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endmodule
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// Rising edge DFF with async active-low reset
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module \$_DFF_PN0_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
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endmodule
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// Rising edge DFF with async active-low set
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module \$_DFF_PN1_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
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endmodule
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// Rising edge DFF with sync active-high reset
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module \$_SDFF_PP0_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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sdffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
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endmodule
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// Rising edge DFF with sync active-high set
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module \$_SDFF_PP1_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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sdffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
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endmodule
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// Rising edge DFF with sync active-low reset
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module \$_SDFF_PN0_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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sdffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
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endmodule
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// Rising edge DFF with sync active-low set
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module \$_SDFF_PN1_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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sdffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
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endmodule
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// Falling edge DFF
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module \$_DFF_N_ (D, C, Q);
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input D;
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input C;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
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endmodule
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// Falling edge DFF with async active-high reset
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module \$_DFF_NP0_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffnr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
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endmodule
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// Falling edge DFF with async active-high set
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module \$_DFF_NP1_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffns _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
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endmodule
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// Falling edge DFF with async active-low reset
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module \$_DFF_NN0_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffnrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
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endmodule
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// Falling edge DFF with async active-low set
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module \$_DFF_NN1_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffnsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
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endmodule
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// Falling edge DFF with sync active-high reset
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module \$_SDFF_NP0_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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sdffnr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
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endmodule
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// Falling edge DFF with sync active-high set
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module \$_SDFF_NP1_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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sdffns _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
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endmodule
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// Falling edge DFF with sync active-low reset
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module \$_SDFF_NN0_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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sdffnrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
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endmodule
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// Falling edge DFF with sync active-low set
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module \$_SDFF_NN1_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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sdffnsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
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endmodule
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