Krystine Sherwin 5d3ed5a418 analogdevices: Extra tests ... `mem_gen.py` based on quicklogic tests. Remove BUFG from `lutram.ys`. Extra `sync_ram_sp` models in `arch/common/blockram.v`. Add analogdevices to main makefile tests. Not all the other tests are passing, but that's fine for now.		2026-03-05 05:37:13 +00:00
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memory_attributes	…
add_sub.v	…
adffs.v	Allow initial blocks to be disabled during tests	2021-11-13 21:53:25 +01:00
blockram.v	analogdevices: Extra tests	2026-03-05 05:37:13 +00:00
blockrom.v	tests: fix blockrom.v driver conflict	2024-12-02 16:56:42 +01:00
counter.v	Fix files with CRLF line endings	2021-06-09 12:16:33 +02:00
dffs.v	Allow initial blocks to be disabled during tests	2021-11-13 21:53:25 +01:00
fsm.v	Fix files with CRLF line endings	2021-06-09 12:16:33 +02:00
latches.v	…
logic.v	…
lutram.v	…
mul.v	intel_alm: Add multiply signedness to cells	2020-08-26 22:50:16 +02:00
mux.v	…
shifter.v	Allow initial blocks to be disabled during tests	2021-11-13 21:53:25 +01:00
tribuf.v	…