mirror of https://github.com/YosysHQ/yosys.git
40 lines
572 B
Plaintext
40 lines
572 B
Plaintext
# Simple Dual Port
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# Supported:
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# SDP_4096x05
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# SDP_2048x10
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# SDP_1024x40
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# Ignored:
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# SDP_2048x09
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ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ {
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option "ENABLE_WIDTH" "BIT" {
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abits 12;
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widths 5 10 global;
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byte 1;
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cost 1;
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}
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option "ENABLE_WIDTH" "BYTE" {
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abits 10;
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width 40;
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byte 8;
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cost 4;
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}
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# Unclear if/how RBRAM is initialized, default SIM_INIT_BEHAVIOUR is UNINITIALIZED
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init none;
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port sr "R" {
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clock anyedge;
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clken;
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}
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port sw "W" {
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clock anyedge;
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clken;
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}
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}
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# Single Port
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# SP_1024x20
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# Dual Single Port
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# SP2_1024x09
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# SP2_2048x05
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