yosys/tests
Emil J 46fbed6e6f
Merge pull request #5525 from YosysHQ/emil/fix-xaiger2-empty-cell-input
aiger2: fix empty cell input
2025-12-04 16:47:53 +01:00
..
aiger Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
alumacc
arch pyosys: __getitem__ for supported classes 2025-11-19 18:09:41 +02:00
asicworld Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
bind Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
blif Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
bram
bugpoint raise_error: don't rely on module ordering in test 2025-09-16 15:47:16 +02:00
cxxrtl tests: replace CC and gcc with CXX and g++ 2025-09-11 16:50:23 +02:00
errors
fmt tests: replace CC and gcc with CXX and g++ 2025-09-11 16:50:23 +02:00
fsm
functional Undo more unnecessary changes 2025-11-29 16:17:27 -08:00
hana Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
liberty filterlib, read_liberty: add loopy retention cell formal equivalence test 2025-11-21 00:57:54 +01:00
lut Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
memfile
memlib Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
memories Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
opt Merge pull request #3991 from adrianparvino/alumacc-sign 2025-10-08 13:02:10 +02:00
opt_share
peepopt Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
proc Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
pyosys pyosys: __getitem__ for supported classes 2025-11-19 18:09:41 +02:00
realmath
rpc Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
rtlil Add CONST_FLAG_UNSIZED 2025-11-07 17:45:07 +13:00
sat fix(parse): #5234 adjust width of rhs according to lhs 2025-09-16 15:24:23 +02:00
sdc sdc: error on unknown getters 2025-11-19 15:26:02 +01:00
select Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
share
sim Revert sim's cycle_width default back to 10, but keep -width option 2025-10-20 14:40:05 +02:00
simple Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
simple_abc9 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
smv
sva
svinterfaces tests/svinterfaces: re-chmod test script 2025-10-15 09:49:53 +13:00
svtypes tests: remove -seq 1 from sat with -tempinduct where possible 2025-09-08 18:04:32 +02:00
techmap aiger2: add crash test 2025-12-02 15:30:02 +01:00
tools tests: replace CC and gcc with CXX and g++ 2025-09-11 16:50:23 +02:00
unit Optimize IdString operations to avoid calling c_str() 2025-11-12 11:52:04 +01:00
various tests: Tidy up bug3515 2025-11-25 07:35:19 +13:00
verific Set `port_id` for Verific PortBus wires 2025-10-23 20:51:53 +00:00
verilog ignore generated file 2025-11-17 13:35:38 +01:00
vloghtb
xprop
.gitignore Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
gen-tests-makefile.sh