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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 19:19:48 +02:00
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0dd850e6552a74430559ed63c3a9a67aa1c84512
yosys/techlibs
T
History
David Shah 0dd850e655 abc9: Add wire delays to synth_ice40
Signed-off-by: David Shah <[email protected]>
2019-06-26 11:39:44 +01:00
..
achronix
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
anlogic
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
common
Make doc consistent
2019-06-14 10:32:46 -07:00
coolrunner2
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
easic
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
ecp5
Re-enable dist RAM boxes for ECP5
2019-06-24 22:12:50 -07:00
gowin
Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master
2019-04-22 09:09:27 +02:00
greenpak4
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
ice40
abc9: Add wire delays to synth_ice40
2019-06-26 11:39:44 +01:00
intel
Fix formatting for synth_intel.cc
2019-05-09 08:40:05 -07:00
sf2
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
xilinx
Realistic delays for RAM32X1D too
2019-06-25 09:34:28 -07:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
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