yosys/techlibs/quicklogic at 0dafe06cd48a6ec20a2bd26db49cf6ddceb00d1f - yosys - Gitea: Git with a cup of tea

luke/yosys

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Emil J. Tywoniak d071489ab1 hashlib: redo interface for flexibility

2024-12-18 14:49:25 +01:00

..

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

quicklogic: Generate bram_types_sim.v at build time

2023-12-04 18:21:00 +01:00

.gitignore

add dsp inference

2023-12-04 15:52:02 +01:00

Makefile.inc

Fix out of tree build

2023-12-06 09:56:35 +01:00

ql_bram_merge.cc

Fix Windows build by forcing initialization order, fixes #4068

2024-01-02 11:26:48 +01:00

ql_bram_types.cc

add dsp inference

2023-12-04 15:52:02 +01:00

ql_dsp_io_regs.cc

Fix Windows build by forcing initialization order, fixes #4068

2024-01-02 11:26:48 +01:00

ql_dsp_macc.cc

Fix out of tree build

2023-12-06 09:11:51 +01:00

ql_dsp_macc.pmg

ql_dsp_macc: Tune DSP inference code

2023-12-04 15:52:02 +01:00

ql_dsp_simd.cc

hashlib: redo interface for flexibility

2024-12-18 14:49:25 +01:00

synth_quicklogic.cc

quicklogic: Avoid carry chains in division mapping

2024-09-19 12:18:47 +02:00